Inactive

This is a Notice of Proposed Contract Action under FAR Part 12 Acquisition of Commercial Items and FAR Part 13 Simplified Acquisition Procedures. This notice is for information only; a solicitation wi... This is a Notice of Proposed Contract Action under FAR Part 12 Acquisition of Commercial Items and FAR Part 13 Simplified Acquisition Procedures. This notice is for information only; a solicitation will not be issued. THIS IS NOT A REQUEST FOR QUOTATION. No contract will be awarded on the basis of offers received in response to this notice. The associated North American Industry Classification System (NAICS) code is 334516 with a small business size standard of 1,000 employees. The Government intends to negotiate a sole source contract for the purchase of a trapped ion quantum networking and computing electronics control system and software with: M-Labs Limited 5/F., Yat Chau Building 262 Des Voeux Road Central Hong Kong POC: Sebastien Bourdeauducq, Scientific Sales Engineer, sb@m-labs.hk Specifications details are: Kasli FPGA carrier (QTY = 2) 3 SFP connectors for Ethernet (if Kasli is the master) and DRTIO (one upstream, two downstream). Each with a LED. SFP1: Ethernet in stand-alone (if Kasli is master), DRTIO upstream otherwise SFP2: DRTIO downstream SFP3: DRTIO downstream or special purpose. 1 micro USB for JTAG, serial console, I2C 1 SMA to the clock recovery and clock distribution chip used as RTIO reference clock input in master/stand-alone mode (10 dBm sine/square) FBarrel connector for +12V power, used for Kasli and passed through to the EEM IDCs. Compatible with locking barrel connectors for increased ruggedness.Eight EEM (0-7) available as 30 pin IDC connectors on Kasli Four EEM (8-11) available on the 96 pin DIN 41612 connector DIN 41612 96 position connector to backplane. Hosts 8 EEMs using standard EEM headers Up to 4 EEMs via backplane 1 SATA (wired as master/host) connected to a transciever SATA1 ("host" pinout, not "disk"/"reversed"): DRTIO downstream or special purpose 4 MMCX outputs with the RTIO reference frequency Port 4 of the FT4232H available on an optional pin header FPGA JTAG 3 USER_LEDs XC7A100T-2FGG484I FPGA, DDR3 RAM, SPI flash a clock recovery and distribution network USB connectivity with four virtual ports four high speed 6 GB/s transcievers for Ethernet and DRTIO, and up to 12 EEM ports for Eurocard Extension modules 8 channel SMA TTL card (QTY = 10) Extension module (EEM) supplying 8 digital IOs via front-panel BNCs. Occupies one EEM port Two banks of four channels each Each bank with individual ground isolation Per-bank switchable direction via on-board switches or I2C Per-channel switchable 50 Ohm termination with LED indicators Output channels can supply >2V into 50 Ohm loads Output channel impedance: 50 Ohm Short circuit tolerance: infinite Minimum pulse width: 3ns Max 150 MHz toggle rate with 50% duty cycle IO direction switched in groups of 4 channels Panel width: 8HP Urukul 4-channel DDS card AD9910 (QTY = 4) DDS Two variants of Urukul are available with different DDS chips: AD9912 and AD9910 Output frequency (-3 dB): <1 to >400 MHz Frequency resolution: AD9912: ~8 µHz (47 bit) -- see AD note AD9910: ~0.25 Hz (32 bit); see also #210 for an extension of the frequency resolution using the DRG) Frequency update rate using the single-width SPI bus: > 500 kHz burst aggregate, TBC Phase offset resolution: 14 bit (AD9912), 16 bit (AD9910) Digital amplitude (ASF) resolution: 14 bit (AD9910 only) DAC full scale current resolution: 10 bit (AD9912), 8 bit (AD9910) DAC full scale current slew rate: ~6 mA/20 µs, 100 ns/LSB (AD9912) #205 Temporal resolution, FTW/POW/ASF updates: 4 ns (IO_UPDATE on a SERDES TTLOut) (TBC) OSK: not supported DRG control pins: not supported Profile (using the AD9910 PROFILE pins): ganged and exposed in the shift register RF signal chain Anti-Aliasing: The lowpass can be replaced by a custom discrete filter. This allows usage of the second or third Nyquist zones. Digital step attenuator resolution: 0.5 dB Digital step attenuator range: 0 to -31.5 dB Digital step attenuator glitch duration: 100 ns Nominal max output power (1dB compression from expected attenuator/ASF/FSC setting due to pre-amplifier): 10 dBm Temporal resolution RF switch: 1 ns (limited by FPGA OSERDES/ARTIQ TTLOut resolution) RF switch speed: 100 ns rise to 90 % RF switch isolation: 70 dB Jitter RF switch: < 1 ns, TBC RF switches controlled by dedicated LVDS lines on EEM1 and by shift register (logical OR) Crosstalk: -84 dB with victim RF switch open, -110 dB with victim switch closed Cross-channel-intermodulation: -90 dB Harmonics: at 6 dBm: -40 dB, -54 dB; at 10.5 dBm: -34 dB, -28 dB Noise/Stability Phase noise/stability (100 MHz ref in, 1 GHz DDS PLL, 81 MHz output): 0.1 Hz: -85 dBc/Hz 1 Hz: -95 dBc/Hz 10 Hz: -107 dBc/Hz 100 Hz: -116 dBc/Hz 1 kHz: -126 dBc/Hz 10 kHz: -133 dBc/Hz 100 kHz: -135 dBc/Hz 1 MHz: -128 dBc/Hz 10 MHz: -149 dBc/Hz AM-to-PM coefficient: < 5 deg/dB (TBC) Amplitude temperature coefficient: < 0.01 dB/K TBC Amplitude noise/stability: TBD RF switch turn-on chirp: <0.1 deg/s (excluding the first ~µs) Clock input Input frequency: 10 MHz to 1 GHz (TBC, depending on PLL/clocking configuration) Input power: 10 dBm nominal (TBD to TBD dBm) Source: External SMA, internal MMCX (from Kasli or Clocker), or on-board XO Selection between MMCX and XO: on board jumpers Selection between MMCX/XO and SMA: software Default design is 1 GHz DDS clock from 125 MHz or 100 MHz reference frequency input using the DDS PLLs On-board divider divides the input clock by 1, 2 or 4 (programmed by the CPLD). Default is 1 for the AD9912, 4 for the AD9910. AD9912 PLL 11 - 200 MHz (2.75 - 800 with 1/4 divider), 4x - 66x ratio even AD9910 PLL accepts clocks between 3.2MHz and 60MHz (12.8 and 240 with divider), PLL multiplication factors between 12 and 127 (48 and 508 with divider) Environmental Air flow: > 50cm/s (from thermal simulation, #321), TBD Power consumption: 7 W (AD9910)/6.5 W (AD9912) with 1 GHz PLL, 4x400 MHz, 10.5 dBm, 52 C DDS temperature sitting on bench Front panel Each channel: SMA RF output Green LED indicating RF output enabled Red LED indicating DDS sychronization/PLL error or software-controlled function One SMA for the reference frequency input, up to 1 GHz Red LED: over temperature Green LED: power good Sample 8-channel ADC card (QTY = 2) Width: 8HP Channel count: 8 Resolution: 16-bit Sample rate: up to 1.5 MHz Sustained aggregate data rate in single-EEM mode (8 channel readout): ~700 kHz Sustained per-channel data rate in dual-EEM mode (SU-Servo): ~1 MHz Bandwidth: 200kHz -6dB bandwidth for G={1, 10, 100}, 90kHz for G=1000 Input ranges: +-10V (G=1), +-1V (G=10), +-100mV (G=100), +-10mV (G=1000) DC input impedance: Termination off: 100k from input signal and ground connections to PCB ground Termination on: signal 50Ohm terminated to PCB ground, input ground shorted to PCB ground ADC: LTC2320-16 PGIA: AD8253 EEM connectors: power and digital communication supplied by one or two EEM connectors. Grabber camera interface card (QTY = 2) Supports andor iXon Ultra/Life EMCCD 888/897 and Andor X3 cameras PM 10 clock, four data, four control and two serial communications lines. The clock and data lines carry the frame data. They also carry FVAL/DVAL/LVAL (frame, data, line valid flags to describe the shape of the frame and validity of the data). Base transfers 28 bits (4 control and 24 data) per clock cycle. Maximum clock frequency is 85 MHz, line rate on the data lines is 85 MHz * 7 = 595 MHz. Clock speeds and frame format will target the 40 MHz, M=16 bit grey, Base CameraLink (Andor) use case. Needs 1:7 PLL on the clock input for the 1:7 SERDES. The full frame data would be ~16 Mbit. We don't want to store that on FPGA nor do we want to build the DRAM writer for it. Full frame data is also readily available on the "standard" link (USB or Ethernet) through the computer and e.g. Andor SDK, and a good shim layer in Python. For alignment, ion finding and definition of the ROIs use the computer. The gateware will automatically discover the frame dimensions from FVAL/LVAL/DVAL and run/clear row/column coordinate counters accordingly. Frame dimensions will be limited to K=12 bits (4096 rows and columns). To process the data, it is streamed through and N>=16 "ROI engines". N=32 if possible. Each ROI engine gates on one rectangular pixel region and accumulates pixel values for each frame. The ROI engines operate independently and can be overlapping. The accumulators need to be 2*K + M = 36 bit wide. After the frame, the accumulated value is pushed as an RTIO input event if the ROI region is enabled. One RTIO input channel for all ROI engines. The ROI engines sensitivity areas are configured through a single RTIO port (or even through slower non-RTIO/out-of-band means). N addresses, each 4x12 bits ROI data. The RTIO input submission is gated (per ROI engine) by a N-bit gate RTIO port, analogous to the TTL input gate. This allows suppression of spurious input events e.g. during alignment or cleaning frames. The kernel CPU can use the values to perform dark frame subtraction, calibration, thresholding, bayesian analysis, calculate moments, and otherwise handle the data. Zotino 32 channel DAC card (QTY = 2) 32-channel, 16-bit DAC EEM with an update rate of 1MSPS (divided between the channels). Width: 4HP Channel count: 32 Resolution: 16-bit Update rate: 1MSPS, which may be divided arbitrarily between the channels Analogue bandwidth: 3rd-order Butterworth response with 75kHz cut-off; ?V/s slew-rate Output voltage: ±10V Output impedance: 470Ohm in parallel with 2.2nF DAC: AD5372BCPZ EEM connectors: power and digital communication supplied by a single EEM connector. Power consumption: 3W without load, 8.7W with max load on all channels. Temperature stability: OpAmp self-heating is about 25C. 0.2ppm/C or 4ppm. BNC-IDC (QTY = 8) Adapter for routing analog potentials from Zotino IDC headers to BNC. Eurocard chassis Chassis and mounting hardware (QTY = 2) Eurocard rack with 12+1 Eurocard slots Assembly, bitstream generation based on existing ARTIQ features, and testing (QTY = 2) Testing done to ensure workable software and hardware upon delivery for controlling trapped ion quantum information system M-labs (ARTIQ) is the only known manufacturer of a complete ion trapping quantum information control system with hardware and software to program trapped ion system. This system includes TTL channels, DDS channels, hardware for grabbing images from EMCCD cameras currently being used at the Air Force Research Lab, Analog to digital converters, digital to analog converters, and a programmable (with python) FPGA chip capable of running experiments at ~100 MHz rates. This is the only known manufacturer of unified hardware and software control for trapped ion quantum computing. This is a notice of proposed contract action and not a request for competitive proposals; however, all responsible sources may submit a capability statement or proposal, which shall be considered by the agency. All inquiries should be sent by email to richard.childres@us.af.mil. Responses must be submitted by the date/time listed on the notice. Any response to this notice must show clear and convincing evidence that competition would be advantageous to the Government in future procurements. Responses received will be evaluated; however a determination by the Government not to compete the proposed procurement based upon responses to this notice is solely within the discretion of the Government. The Government anticipates an award date on or before 31 JUL 2020. A Sole Source Justification will be attached to the subsequent Notice of Award in accordance with applicable regulation. “Notice to Offeror(s)/Suppliers(s): Funds are not presently available for this effort. No award will be made under this solicitation until funds are available. The Government reserves the right to cancel this solicitation, either before or after the closing date. In the event the Government cancels this solicitation, the Government has no obligation to reimburse an Offeror for any costs.”