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NIST is seeking information from vendors capable of providing customized CMOS wafers for a wafer-scale 0.18um CMOS chip fabrication process. The CMOS wafers were originally designed to be used in deve... NIST is seeking information from vendors capable of providing customized CMOS wafers for a wafer-scale 0.18um CMOS chip fabrication process. The CMOS wafers were originally designed to be used in developing a measurement and application testbed for novel electronic devices. The wafers in question should meet the following specifications: Process flow shall be 0.18 um 1.8/3.3 V 1P6M CMOS Logic Process or equivalent. The following mask/process options shall be used for the fabrication process: Single-poly and up to six metal layers Dual gate: 1.8V core and 3.3V I/O, including both thick and think gate transistors Bipolar transistors Medium VT transistors Cobalt silicided source, drain and gate Shallow trench isolation Super steep retrograde twin well Deep N-well Aluminum metallization with tungsten plug FSG inter-metal dielectric Metal-Insulator-Metal (MIM) capacitor as an option, with custom placement of MIM caps between metal layers. Poly resistors NIST post-processing of the finished wafers requires that the process be stopped after planarization of the fifth layer and before the top metal layer is applied, leaving exposed vias on a planarized surface. Vendor MUST DELIVER WAFERS STOPPED AT THIS PROCESS STEP. Interested parties shall describe the capabilities of their organization as it relates to the requirement described above. US manufacturers of same or similar items are encouraged to respond.