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The California Institute of Technology’s (Caltech’s) Jet Propulsion Laboratory (JPL), located at 4800 Oak Grove Drive, Pasadena, CA 91109, is issuing the subject RFI to obtain information to assess cu... The California Institute of Technology’s (Caltech’s) Jet Propulsion Laboratory (JPL), located at 4800 Oak Grove Drive, Pasadena, CA 91109, is issuing the subject RFI to obtain information to assess current industry manufacturing and technical capabilities and receive ROM cost and schedule estimates supporting the development of various SOSA S3C & HPSC based turn-key products. Glossary PIC = Plug-In Card CFE/CFS = Core Flight Executive / Core Flight Software SOSA = Sensor Open System Architecture S3C = SOSA Space Sub Committee F’ = F prime JPL Open-source flight software framework SBC = Single Board Computer PSC = Power Supply Card Purpose NASA is seeking to spur the development of an industry wide ecosystem of standardized interoperable cards that can be used to implement complete spacecraft avionics systems based on the SOSA™ S3C profiles. To guarantee interoperability the SOSA™ Space Subcommittee, comprising members from NASA, USSF and industry, have been working on a spacecraft avionics standard derived from the VITA 78 (Space VPX) specification. Initial elements of the standard are documented in the recently released SOSA Standard Snapshot 3(see SOSA Space Appendix), which has garnered broad industry support. The purpose of this RFI is to gather information which could eventually lead to a JPL RFP soliciting the development of one or more S3C SpaceVPX compliant development kit(s) for both commercial industry and government organizations. To this end, information is requested related to integrated development kits, as well as constituent products that can be included in a development kit (i.e. PICs, PSCs, software). NASA is proposing SBCs in this development kit be based on the High-Performance Spaceflight Computing (HPSC) processor, currently in development with Microchip Technology Inc. in a partnership with NASA and JPL, using the SOSATM S3C SBC Slot Profile. Overview The development kit is part of a broader NASA effort to advance space-based computing through the Sensor Open System Architecture (SOSA™) and its Space Subcommittee (S3C). The SOSA™ S3C aims to create a standardized and interoperable framework for space systems, encouraging collaboration among government agencies, industry, and academia to develop interoperable hardware and software solutions. This effort will support the creation of turn-key systems for testing, development, and flight, enabling more efficient and cost-effective space mission planning and execution. Background NASA’s High Performance Spaceflight Computing (HPSC) project is delivering purpose-built space computing technology for high performance computing. The High-Performance Spaceflight Computing (HPSC) project, a collaboration between NASA and Microchip Technology Inc., is finalizing a cutting-edge, radiation-hardened flight processor that offers 100 times the computational power of current spaceflight computers. It will provide high performance AI dataflow processing with scalable vector computing capabilities that are critical for the science and autonomy needs of future advanced space systems. HPSC is Fault-Tolerant: specially designed to survive in space and contains features that ensure it can operate correctly and provide reliable results in the harshest of natural space environments. This ensures the most critical operations such as: Robotically landing on or flying on another planet Supporting astronauts far from the earth Operating near small bodies in the outer solar system HPSC builds on Industry-Standards. The core of the HPSC design is an industry standard RISC-V based CPU bundled with significant fault and radiation tolerance, and a full security suite as well as all the software required to run it. The HPSC also includes a suite of features and industry-standard interfaces and protocols not previously available for space applications. HPSC offers a variety of advanced capabilities: Space-grade 64-bit Processor Architecture: Includes eight SiFive RISC-V X280 64-bit CPU cores supporting virtualization and real-time operation, with vector extensions that deliver up to 2 TOPS (int8) or 1 TFLOPS (bfloat16) of vector performance for implementing AI/ML processing for autonomous missions. High-speed network connectivity: Includes a 240 Gbps Time-Sensitive Networking (TSN) Ethernet switch for 10GbE connectivity. Also supports scalable and extensible PCIe® gen 3 and Compute Express Link™ (CXL™) 2.0 with x4 or x8 configurations and includes RMAP-compatible SpaceWire ports with internal routers. Low-latency data transfers: Includes Remote Direct Memory Access (RDMA) over Converged Ethernet (RoCEv2) hardware accelerators to facilitate low-latency data transfers from remote sensors without burdening compute performance – maximizing compute capabilities by bringing data close to the CPU. Platform-level defense grade security: Implements defense-in-depth security with support for post-quantum cryptography and anti-tamper features. High fault-tolerance capabilities: Supports Dual-Core Lockstep (DCLS) operation, WorldGuard hardware architecture for end-to-end partitioning and isolation, and an onboard System Controller for fault monitoring and mitigation. Flexible power tuning: Includes dynamic controls to balance the computational demands required by the multiple phases of space missions with tailored activation of functions and interfaces. For more information on the HPSC capabilities please contact Microchip Technology Inc. (tao.lang@microchip.com) SOSA™ S3C/HPSC Development system Overview The SOSA™ S3C/HPSC development system comprises a lab-grade hardware suite and accompanying software that, together, offer a versatile platform for developing and testing hardware and software for space applications. These systems should have a viable path to and should be form, fit, and function equivalent to an eventual flight model. Below are some examples use cases that highlight the potential applications and benefits of the development system: Development of Flight Software: Use Case: Engineers can use the development system to develop and validate flight software such as NASA’s Core Flight Executive/Core Flight Software (CFE/CFS) and the F prime (F’) framework developed by JPL. Benefits: This allows for thorough testing in a controlled environment, ensuring that the software performs reliably under different conditions. Hardware Integration and Testing: Use Case: The development system can be used to integrate various PICs and other infrastructural hardware elements into a multi-slot S3C chassis. This includes components like PSCs, SBC, data storage cards, IO expanders, and more. Benefits: This facilitates comprehensive hardware testing, ensuring compatibility and functionality of different components within the system. Prototype and Engineering Model Development: Use Case: The system can support the development of prototypes and engineering models of flat sats and similar flight systems. These prototypes can be tested for various parameters, including performance, reliability, and resilience to environmental factors. Benefits: Early identification and resolution of potential issues, leading to more robust and reliable flight systems. Educational and Training Purposes: Use Case: Academic institutions and training centers can use the development system to educate students and professionals about space system design and testing. Benefits: Provides hands-on experience with real-world hardware and software used in space missions, enhancing the skills and knowledge of the next generation of aerospace engineers. Collaborative Development and Standardization: Use Case: The system can be used by different organizations (e.g., NASA, JPL, AFRL, Aerospace primes) to collaboratively develop and refine standards for space systems, such as those defined by the SOSA™ S3C. Benefits: Promotes interoperability and standardization across different space missions and organizations, leading to more efficient and cost-effective development processes. Performance Benchmarking and Validation: Use Case: The development system can be used to benchmark the performance of various hardware and software configurations, ensuring that they meet the required specifications for space missions. Benefits: Provides validated performance data, helping stakeholders make informed decisions about hardware and software choices before making large investments in hardware, software, and systems development. Custom Configuration and Flexibility based on industry standards: Use Case: Users can configure the system with different PICs and software elements to suit specific mission requirements. The development system supports various operating systems, including Linux variants and real-time operating systems like VxWorks. Benefits: Offers flexibility to tailor the system to specific needs, ensuring that it can be adapted to a wide range of applications based on an industry standard platform which reduces time-to-market and time-to-flight, reduces project cost and reduces project risk. These examples demonstrate the versatility and utility of the SOSA™ S3C/HPSC development system, highlighting its potential to significantly advance the development and testing of space systems. For more detailed information on the HPSC project and its applications, refer to the following sources: High Performance Spaceflight Computing (HPSC) - NASA (Link below) SOSA™ S3C/HPSC Development Kit Specifications Turn-key Lab Development System/Testbed (not for environmental or flight testing) comprising: a. Multi-slot S3C chassis with cards (examples: PSC, HPSC SBC, Data Storage, SSD, External I/O), Operating System with appropriate test and debug capability for basic software development and hardware testing (of the delivered unit), and chassis management software. b. The initial product could feature a 3U 8-slot backplane/chassis and a single PSC and SBC with appropriate software. c. The initial product may consist of non-flight parts but will include a pathway to upgrade to flight-certified components. d. The initial product should incorporate either a Linux variant or one of the standard high-end real-time operating systems like VxWorks, along with compilers, standard debuggers, and other development system elements for the HPSC SBC. The delivered chassis should include interfaces for integrating other PICs and software elements, IPMC functions, and chassis managers. e. A user’s guide should be provided. 2. Elements (building blocks) of a SOSA S3C system that allow users to configure their own hardware and software solutions, including the turn-key system above and potentially other PICs as defined in the standard. 3. Turn-key Testbed Support Equipment to complement the SOSA S3C system. This may include rack hardware, development computers and monitors, network support equipment, additional capacity for analysis equipment, cooling solutions, and power management. Summary of SOSA™ S3C/HPSC Development Kit NASA seeks information leading to the potential development, in a public-private partnership, of a SOSA S3C/HPSC development system and testbed. Both input from potential developers and potential users is requested. The development kit should encompass: Hardware, e.g., PSC/PICs and ancillary infrastructural hardware elements. Software, e.g., Full package to support SOSA S3C chassis and cards as well as configuration software and any software needed for the Testbed support equipment. To identify potential industries and partners NASA seeks the below information: Technical Specifications and Costing: Turnkey System: Provide concept specifications, ROM (Rough Order of Magnitude) costing, and deployment schedule estimates for a complete SOSA S3C/HPSC development system and testbed. Constituent Elements: Technical concept specifications, ROM costing, and integration schedules estimates for individual PICs, software and components needed for assembly. 2. Alternative Approaches: Propose possible alternative configurations or technologies that can reduce costs and improve utility while meeting the primary objectives outlined. 3. Provider Capabilities Identify your ability to provide PICs or fully integrated development systems. 4. Funding Specify schedule estimates, estimated resource requirements, and potential for cost sharing versus the need for NASA Non-Recurring Engineering (NRE) support. 5. Market Size and Marketing Approach: Provide an analysis of the market size and growth potential within the space sector for the SOSA S3C/HPSC system and testbed. Outline your marketing approach, including strategies to penetrate non-space markets such as defense, broader aerospace, and industrial automation. 6. Storefront/Customer Support Approach: Describe your storefront or online platform where customers can access information, place orders, and receive support for aerospace systems. Detail your customer support strategy, including technical assistance, training programs, and maintenance services. 7. Manufacturing Capability: Detail any manufacturing capabilities relevant to producing components or systems for aerospace applications, including the following: Quality Assurance: Explain your quality control measures and certifications (e.g., AS9100) ensuring the reliability and performance of aerospace components. Electronic Testing: Outline your capabilities in electronic testing and verification to meet stringent aerospace requirements. Mechanical/Electronic Packaging Design: Describe your expertise in designing robust and space-efficient mechanical and electronic packaging solutions suitable for aerospace environments. Additional Information The requested information is for preliminary planning purposes only and does not constitute a commitment, implied or otherwise, that JPL will solicit you for such procurement in the future. Neither JPL nor the Government will be responsible for any costs incurred by you in furnishing this information. The North American Industry Classification System (NAICS) code and description for this acquisition is 334511 Search, Detection, Navigation, Guidance, Aeronautical, and Nautical System and Instrument Manufacturing. The size standard for this NAICS code is 1,350 employees. Additional information can be found here: https://www.sba.gov/document/support-table-size-standards. Perspective subcontractors are advised that any information provided shall be deemed to be furnished with unlimited rights to JPL, with JPL assuming no liability for the disclosure, use or reproduction of such data. Please provide the requested information by January 31, 2025 via email to: JPL Subcontracts Manager, gabriel.obregon@jpl.nasa.gov. If you have any questions about this RFI, please contact the undersigned.